The present invention relates to a method for forming self-aligned, small geometry, shallow junction depth MOS monolithic integrated circuits by implanting the n.sup.+ /p.sup.+ source and drain regions through a silicon layer. The process sequence is also adaptable to the formation of beneficial structures, including LDD (lightly doped drain) structures, guard band structures and gate oxide sidewall spacers.
With the increasing implementation of small geometry, highly dense MOS monolithic integrated circuit components, various structural and operational problems have combined to limit device performance and manufacturing yields and, thus, the achievable minimum feature sizes and maximum densities. Among the most difficult of the problems are those collectively termed short-channel effects, which include hot carrier injection into the gate oxide and/or substrate, source-drain punch-through, reduced breakdown voltage and impact ionization. In hot carrier injection, for example, electrons are permanently injected into the gate oxide by the strong electric field which is created by the narrow channel region adjacent the drain and, as a consequence, alter the threshold voltage of the device. In addition to the short-channel effects, overlap between the gate electrode and the source and drain results in parasitic capacitance known as Miller capacitance, which decreases high frequency response and operational speeds.
As channel lengths and other device dimensions are reduced in VLSI monolithic integrated circuits, new device structures such as LDD structures, guard band structures, and gate sidewall dielectric spacers have been implemented to reduce the short-channel effects and to optimize transistor characteristics such as high transconductance, high breakdown voltage, fast operating speeds and device densities. In particular, the LDD structure is a shallow, preferably self-aligned n.sup.- or p.sup.- region formed between the MOSFET channel and the n.sup.+ or p.sup.+ source and drain diffusions. Except when bidirectional current is used, the LDD structure is needed only for the drain, not the source, but LDD structures are typically formed for both the source and the drain diffusions to avoid the use of an additional masking step. The LDD structure increases breakdown voltage and reduces impact ionization and hot electron emission by spreading the high electric field at the drain pinch-off region into the associated n.sup.- or p.sup.- region.
Several approaches are available for implementing LDD structures. One LDD approach is disclosed in Goto et al., "A New Self-Aligned Source/Drain Diffusion Technology From Selectively Oxidized Polysilicon", IEDM Technical Digest, Paper 25.3, 1979, pp. 585-588. Goto et al. discusses the "conventional process" of implanting source and drain regions through a precisely dimensioned polysilicon layer, and discloses an alternative approach for forming short channel, flat surface NMOS LSI's having self-aligned contacts and self-aligned source and drain diffusions using selective oxidation of a phosphorus-doped polysilicon layer. In the Goto et al. process, the field oxide and gate oxide are grown, contact cuts are made in the gate oxide, then a doped polysilicon layer is deposited and a nitride definition mask is defined and patterned. An oxidation step is then applied with the nitride in place to selectively and fully convert the polysilicon outside the nitride mask into an oxide interlayer which surrounds the gates, interconnects and contacts. In addition to the simultaneous conductor and interlayer formation, the oxidation drives-in the source, drain and contact regions. A relatively thin CVD oxide is then deposited to complete the dielectric interlayer, which provides self-aligned contacts for metallization. Alignment of the contact mask for the dielectric interlayer is not critical because only the CVD oxide is etched to form contact cuts and the cuts are not sufficiently deep to reach the n.sup.+ regions.
Muramoto et al., "A New Self-Aligning Contact Process for MOS LSI", IEDM Technical Digest, 1978, pp. 185-188, is similar to Goto et al. in selectively converting the polysilicon gate/contact layer into an isolation oxide to define contact cuts in an intermediate dielectric layer. Initially, the field oxide and gate oxide are grown and contact cuts are opened in the gate oxide, then a doped polysilicon layer is deposited and a nitride definition mask is deposited and patterned over the gate substrate contact and interconnect areas. The poly is etched halfway through in the unmasked regions. Graded n.sup.+ n.sup.- LDD source/drains are formed by a combination of ion implantation through the remaining polysilicon and gate oxide and by diffusion from the doped polysilicon. The nitride is then removed except at the gate, interconnect and contact areas and the poly is selectively oxidized with the nitride in place. In the unmasked, partially etched-through, thin poly regions, the poly is completely converted to oxide, whereas in the newly unmasked interconnect areas, partial conversion provides an insulative oxide layer formed over the poly conductors. Consequently, the oxidation and conversion completes the formation of poly gates interconnects and contacts which are surrounded by the oxide and, in the case of the interconnects, covered by the oxide interlayer. Also, the nitride prevents oxidation of the top surface of the poly and automatically defines contact "cuts" to the poly. The first nitride etch, the partial poly layer etch, and the nitride mask removal are done by plasma reactive sputter etching using C.sub.2 F.sub.6 /C.sub.2 H.sub.4 /O.sub.2 gas system. With this system, double-layered nitride and polysilicon can be etched successively and nitride on poly or oxide can be selectively etched, by changing the gas mixture ratio.
Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field Effect Transistor", IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, pp. 1359-1367, August 1980, describes LDD device design and characteristics and, in pertinent part, describes a conventional planar silicon gate processing technique for LDDFETS. After forming the field oxide and gate oxide, an oversized gate stack comprising the poly gate and an overlying oxide-nitride mask is formed and used as a mask during implanting of the n.sup.+ source and drain through the gate oxide layer. A wet etch or plasma etch is then applied to undercut the gate to its final dimension, then the oxide-nitride mask is stripped and an n.sup.- implant is applied to form the LDD regions self-aligned with the channel and the n.sup.+ source/drain diffusions.
Jecmen, U.S. Pat. No. 4,198,250, issued Apr. 15, 1980, applies a silicon dioxide gate overhang mask and uses the n.sup.+ implant step to implant the n- LDD structure through the gate oxide layer. The oxide overhang mask is defined by wet chemical undercutting of the supporting doped polysilicon gate to the desired gate dimensions beneath the mask, then the n.sup.+ source/drain implant is applied. During the n.sup.+ implantation, the overhang mask partially blocks the ion so that the implant also forms shallow, lightly doped n.sup.- LDD regions self-aligned with the channel and the n.sup.+ source and drain regions.
Commonly assigned (to NCR Corporation) U.S. Pat. Nos. 4,182,023, issued Jan. 8, 1980, to Cohen et al., and 4,149,904 issued Apr. 17, 1979 to Jones, both use a photoresist overhang mask to precisely align the source and drain with the silicon gate and minimize gate overlap or Miller capacitance. In both patents, the gate is overetched/undercut a predetermined distance beneath a photoresist overhang mask. In the Cohen et al. the aligned source/drain structures are then formed by predeposition (by implantation or diffusion), followed by heating to drive the source/drain into coincidence with the gate boundaries. In the Jones the gate oxide layer is left intact and the source/drain are formed by ion implantation, using controlled lateral scattering during the implant to align the source/drain structures with the gate electrode.
As indicated by a review of the above-discussed articles and patents, the effectiveness of lightly doped source-drain structures in improving device performance and eliminating problems associated with small geometry high density monolithic integrated circuits is known. However, in implementing these beneficial structures, it is difficult to avoid process complexity. It is, accordingly, an object of the present invention to implement a MOS process which incorporates the characteristics of self-aligned lightly doped drain structures, yet is relatively simple and is adaptable to the incorporation of other beneficial structures.
It is also an object of the present invention to provide a simplified MOS process in which the n.sup.+ /p.sup.+ source and drain are implanted through a silicon blocking layer covering the source/drain, to provide a shallow controlled implant which, in the case of boron in particular, is free of channeling effects.
It is another object of the present invention to provide a MOS process in which the lightly doped drain structure can be formed by lateral scattering of the implanted species by the silicon source/drain blocking layer.
It is also an object of the present invention to provide a MOS process which has the above advantages and which optionally incorporates a guard band diffusion into the drain (and source) structure with or without gate sidewall dielectric structures, in combination with the lightly doped drain structures, using a minimum of additional process steps, for the purpose of minimizing short-channel effects and Miller capacitance.